1. Field of the Invention
The present invention relates to a mapping apparatus, and, more particularly, to an apparatus for mapping DS serial data to VC parallel data.
2. Background of the Related Art
Generally, a synchronous digital hierarchy (SDH) system performs a mapping operation for an asynchronous signal according to an ITU-T recommendation. That is, the SDH system performs mapping and pointer processing of the asynchronous signal in a virtual container. After the mapping and processing are complete, the SDH system multiplexes the signal to form a synchronous transmission module STM-1 signal. Therefore, in order to transmit a certain asynchronous signal through the SDH system, a series of processes for changing the corresponding asynchronous signal to an STM-n signal should be performed.
FIG. 1 is a block diagram showing a general SDH system. A plurality of VC11/12 virtual containers (11A–11C) map the asynchronous signals DS-1 and DS-1 E as VC11/12 signals, in a manner determined by control signals J1, mj1, and Plden of an STM-1 counter 15. In addition, a tributary unit group (TUG) circuit (not shown) attaches a path overhead (POH) and a pointer on the VC11/12 signal, which is mapped in the VC11/12 virtual containers 11A–11C, and arranges them as Tributary Unit (TU) signals. After that, the TUG circuit multiplexes the arranged TU signals by a ratio of 1:7 and outputs the TUG signal.
A VC3/4 mapping unit 12A receives the multiplexed TUG signal and the asynchronous signals DS-3, DS3E, and DS4 and maps them as VC3/4 signals, according to address signals J1 and mj1 of the STM-1 counter. VC3/4 mapping units 12B and 12C receive the multiplexed TUG signals and the asynchronous signals DS-3 and DS3E and map them as the VC3 signal, according to address signals J1 and mj1 of the STM-1 counter 15. Address signals J1 and mj1 designate the positions where the asynchronous signals are mapped.
Therefore, an AUG3/4 pointer generating unit 13 pointer processes the VC3 signal and the VC4 signal and outputs the administration unit signals AU3 and AU4. An AU signal mapper 14 multiplexes the AU3 and AU4 signals, output from the AUG3/4 pointer generating unit 13, to form an STM-1 signal.
As described above, in the series of processes for receiving the asynchronous signals and generating the STM-1 signal, the mapping operations of the VC11/12 virtual container 11A–11C are performed by a buffer disposed as a channel unit, and by a controlling signal inputted into the buffer, as shown in FIG. 2.
FIG. 2 is a detailed block diagram showing respective VC11/12 virtual containers 11A–11C. The VC11/12 virtual containers 11A–11C comprise: an elastic buffer 21 for temporarily storing the asynchronous signals DS-1 and DS-1 E, that is, serial data; a serial/parallel changing unit 22 for changing the serial asynchronous data Sd read from the elastic buffer 21 into parallel asynchronous data Pd; a VC1 mapper 23 for multiplexing the parallel asynchronous signal Pd changed in the serial/parallel changing unit 22, and for outputting VC1/VC12 signals; a VC1 framer 24 fcr controlling the multiplexing operation of the VC1 mapper 23; a write pointer generating unit 25 for generating a write address (WA) of the elastic buffer 21; and a read pointer generating unit 26 for generating a read address (RA) of the elastic buffer 21. The ien and Spen are enable signals of the read pointer generating unit 26 and the serial/parallel changing unit 22, respectively.
When a 1.544 MHz DS-1 signal or a 2.048 MHz DS-1 E signal is inputted, the elastic buffer 21 disposed in the respective channel stores the inputted asynchronous DS-1 or DS-1E signal on a position, which the write address WA of the write pointer generating unit 25 sets.
The VC1 framer 24 is inputted the address signal J1 and mj1 from the STM-1 counter 15 and outputs the enable signals ien and Spen to the read pointer generating unit 26 and to the serial/parallel changing unit 22. Also, the VC1 framer 24 generates mapping control signals V5t, J2t, N2t, and K4t indicating the positions on which the new serial asynchronous signals are mapped. Additionally, the VC1 framer 24 generates the control signals J2dt (8:0), Psr, and Nsr indicating the positions on which the data/null data are inserted periodically.
The read pointer generating unit 26 outputs the read address RA according to the enable signal ien outputted from the VC1 framer 24, and the elastic buffer 21 outputs serial asynchronous signal Sd to the serial/parallel changing unit 22, according to the read address RA. The VC1 framer 24 monitors the difference between the write address WA and the read address RA, and controls the data reading speed by controlling the clock number of the enable signal ien.
Therefore, the serial asynchronous signal Sd read in the elastic buffer 21 is changed into parallel data Pd in the serial/parallel changing unit 22. The VC1 mapper 23 multiplexes the parallel asynchronous signal Pd, changed in the serial/parallel changing unit 22, and outputs VC11/VC12 signal according to the mapping controlling signals V5t, J2t, K4t, J2dt (8:0), Psr and Nsr outputted from the VC1 framer 24.
However, the background art SDH system processes the asynchronous signal by including the elastic buffer 21, the write pointer generating unit 25 the read pointer generating unit 26 and the serial/parallel changing unit 22 in a respective channel. Therefore, as shown in FIG. 1, if the background art SDH system processes 84 channels of DS-1 signals, it needs 84 write pointer generating units, read pointer generating units, and serial/parallel changing units, respectively. In addition, in the background art SDH system, the number of gates needed to implement the respective channels are increased in the case of a multiple channel embodiment, whereby the system structure is complex.
Also, the background art SDH system performs write and read operations of the elastic buffer using the clock signal of the asynchronous signal and the system clock signal, respectively, which are not synchronized with each other. The lack of synchronization creates a system jitter.